In recent years, an integration level in an integrated circuit has greatly increased, which has been accompanied by stricter required conditions imposed on a processing precision such as flatness or smoothness of a mirror-polished wafer surface. In addition, in order to achieve an integrated circuit higher in performance, reliability and product yield, not only a higher mechanical precision, but also better electric characteristics have been required. Especially, an SOI wafer, which is an ideal dielectric isolation substrate, has been used in applications to high frequency and high-speed devices mainly related to mobile communication equipment and medical equipment and further great increase in demand therefor is expected in the future.
An SOI wafer 50, as shown in FIG. 13, has a structure in which an SOI layer 52 (also referred to as a semiconductor layer or an active layer) for forming an element such as a single crystal silicon layer is formed on an insulating layer 54 (also referred to as a buried oxide (BOX) film layer or simply an oxide film layer) such as a silicon oxide film. The insulating layer 54 is formed on a support substrate 56 (also referred to as a substrate layer) and the SOI wafer 50 has a structure in which the insulating layer 54 and the SOI layer 52 are sequentially formed on the support substrate 56. In FIG. 13, reference numeral 60 designates an unbonded region, and reference numeral 62 designates a terrace, which will be described later.
As conventional methods for manufacturing an SOI wafer 50 having the SOI structure in which the SOI layer 52 and the support substrate 56 are made of, for example, silicon and the insulating layer 54 is made of, for example, a silicon oxide film, there are exemplified an SIMOX (Separation by implanted oxygen) method in which oxygen ions are implanted into a silicon single crystal at a high concentration and thereafter the single crystal is subjected to heat treatment at a high temperature to form an oxide film thereon; and a bonding method (an adhering method) in which two mirror-polished wafers are bonded with each other without the use of an adhesive, followed by processing one of the bonded wafers into a thin film.
Since the SIMOX method can controllably determine a film thickness of an active layer portion (an SOI layer) 52 to serve as a device active region by an acceleration voltage in oxygen ion implantation, there is an advantage that a thin active layer high in film thickness uniformity can be easily obtained, whereas there have remained many issues of reliability of a buried oxide (BOX) film (an insulating layer) 54, crystallinity in an active layer, and others.
On the other hand, a wafer bonding method is carried out in such a way that an oxide film (an insulating layer) 54 is formed on at least one of two single crystal silicon mirror-polished wafers, then both wafers are adhered with each other without using an adhesive, then the adhered wafers are subjected to heat treatment (usually at a temperature in the range of 1100° C. to 1200° C.) to strengthen bonding therebetween and thereafter one of the wafers is thinned into a thin film by grinding or wet etching, followed by mirror-polishing the surface of the thin film so as to obtain an SOI layer 52; which leads to advantages that reliability of the buried oxide (BOX) film (an insulating layer) 54 is high and crystallinity of the SOI layer is also good. However, the thus adhered SOI wafer 50 is subjected to mechanical processing such as grinding or polishing into a thin film, and hence the obtained SOI layer 52 have limitations in its film thickness and uniformity.
As a method for manufacturing an SOI wafer 50, it has very recently started to pay attention to a method for manufacturing an SOI wafer by bonding and delaminating an ion implanted wafer. This method is also referred to as an ion implantation delamination method, which is such a technique that two silicon wafers are provided to be ready for use; an oxide film (an insulating layer) is formed on at least one silicon wafer; hydrogen ions or rare gas ions are implanted onto an upper surface of the one silicon wafer; a micro-bubble layer (an enclosed layer) is formed in the interior of the one wafer, the surface onto which the ions are implanted is contacted and adhered with the other silicon wafer through the oxide film interposed therebetween; thereafter by applying heat treatment to the adhered wafers, a part of the one wafer is delaminated with the micro-bubble layer as a cleavage plane for the rest of the one wafer to become a thin film; and heat treatment is further applied to the rest of the adhered wafers to strongly bond the wafers, thereby an SOI wafer being obtained (see JP-A No. 5-211128). According to this method, the cleavage plane is a good mirror-polished surface and the SOI wafer 50 having high uniformity of film thickness of the SOI layer 52 can be obtained with relative ease.
In FIG. 14, further detailed description will be given of the ion implantation delamination method showing one example of a set of main steps thereof. There are provided to be ready for use two starting wafers, that is, a base wafer 56a serving as a support substrate 56 and a bond wafer 52a from which an SOI layer 52 is formed [FIG. 14(a), step 100]. As these wafers, for example, mirror-polished silicon single crystal wafers are used.
An oxide film 54a serving as a buried oxide (BOX) film (an insulating layer) at a later step is formed on a surface of the bond wafer 52a [FIG. 14(b), step 102]. This step is carried out as follows. For execution of this step, for example, thermal oxidation is applied on the bond wafer 52a of a silicon single crystal wafer to form a silicon oxide film on the bond wafer 52a. Incidentally, the formation of the oxide film may be performed on the surface of the base wafer 56a, not on the surface of the bond wafer 52a. In the illustrated embodiment, the exemplary case where the oxide film 54a is formed on the bond wafer 52a side will be explained.
Then, hydrogen ions are implanted into the bond wafer 52a through the oxide film 54a to form a micro-bubble layer (an enclosed layer) 58 [FIG. 14(c), step 104].
Thereafter, chemical cleaning may be carried out using an H2SO4—H2O2 mixed solution or the like (step 105). The H2SO4—H2O2 mixed solution has been known in a field of wet cleaning with an abbreviation of SPM (Sulfuric Acid-Hydrogen Peroxide Mixture) and is a cleaning solution for removal of organic contaminants.
Then, the bond wafer 52a in which the micro-bubble layer (the enclosed layer) 58 is formed is brought into close contact with the base wafer 56a at room temperature through the oxide film 54a on the surface of the bond wafer 52a onto which the ion implantation has been performed [FIG. 14(d), step 106].
Then, by applying heat treatment (delamination heat treatment) at a temperature of 500° C. or higher, a part of the bond wafer 52a is delaminated at the enclosed layer 58 and the rest of the bond wafer 52a stands in the form of a thin film [FIG. 14(e), step 108]. Next, by applying bonding heat treatment [FIG. 14(f), step 110], the bond wafer 52a in the form of the thin film and the base wafer 56a are strongly bonded with each other through the oxide film 54a interposed therebetween, whereby a wafer 50 having an SOI structure is manufactured.
The SOI wafer 50 manufactured using the adhering method has, at this stage, a sectional structure in which the insulating film (layer) 54 and the SOI layer 52 are separately and sequentially laminated on one main surface of the support substrate 56.
Also, as shown in FIG. 13, the insulating layer 54 and the SOI layer 52 are generally smaller in diameter than the support substrate 56 by a value of the order of several mm, usually about 3 mm (hereinafter, this portion may be referred to as an unbonded region).
In addition, another step may be adopted, in which a surface of the SOI layer 52 of the wafer having the SOI structure is modified and the thickness of the SOI layer 52 is controlled (FIG. 14, step 112). For example, since damage caused by hydrogen ion implantation remains on a surface (a delaminating plane) of the SOI layer 52 of the SOI wafer 50 having the obtained SOI structure, the damage layer is removed by applying polishing with a small polishing stock removal usually called touch polishing. In replacement of touch polishing, by performing heat treatment in an argon gas atmosphere, sacrifice oxidation treatment in which thermal oxidation and removal of an oxide film are conducted to reduce the film thickness of the SOI layer 52 or a combination thereof in a proper way, an SOI wafer 50 having a damage free thin film SOI layer 52 may be manufactured.
In fabrication of devices using the SOI wafer 50, there has been a problem of reducing a product yield of the devices. A cause of this problem is conceivably due to generation of a defect called a void (B) in the SOI layer 52 and an oxide film 54.
As a factor of void generation, for example, in the bonding method (the adhering method), organic matter or particles generated in the steps of manufacturing an SOI wafer may adversely affect the adhering interface to cause a decrease in yield. As another factor, there is conceivable the influence of defects or the like present in the base wafer or the bond wafer.
The problem of the organic matter or the particles can be solved to some extent by performing RCA cleaning or organic matter removing cleaning before wafers are adhered to each other. The RCA cleaning is a typical cleaning method in semiconductor processes using two cleaning liquids of two types, i.e., SC-1 (a liquid mixture of NH4OH/H2O2/H2O) and SC-2 (a liquid mixture of HCl/H2O2/H2O) as bases. According to this cleaning method, impurities such as particles, organic matter, and metallic contaminants can be mainly removed. Organic matter removing cleaning called SPM cleaning may be employed.
As defects or the like present in the base wafer or the bond wafer, a defect called COP due to crystals, a defect due to processing, and the like become issues. These defects can be reduced to some extent by controlling manufacturing conditions. When using a wafer having fewer defects, generation of voids can also be reduced.
By manufacturing an SOI wafer under control of organic matter or particles generated when the wafers are adhered to each other and control of defects on the surfaces of the base wafer and the bond wafer, generation of voids can be reduced. However, there were observed voids that are conceivably due to another new cause. More specifically, as shown in FIG. 15, there was observed a tendency of frequent generation at a specific position of the outer peripheral portion of the SOI wafer 50. FIG. 15 is a schematic view showing results of observation by a laser microscope with a confocal optical system on a part of the outer peripheral portion of the SOI wafer 50. There is called a terrace 62 the boundary between the unbonded region 60 (a portion where the support substrate 56 can be seen when the wafer is observed from the SOI layer 52 side) and the SOI layer 52. A circular void 70 is observed at a portion away from the terrace 62 by a predetermined distance. In particular, the void 70 was generated at a position away from the wafer outer periphery by about 5 mm (145 mm from the center when a wafer having a diameter of 300 mm is used) with reference to the outer peripheral portion of the base wafer. In FIG. 15, the part (b) shows the void 70 generated at a position away from the center by 145.1 mm, the part (c) shows the void 70 generated at a position away from the center by 145.4 mm, and the part (d) shows the void 70 generated at a position away from the center by 144.9 mm.